Continued device scaling requires the formation of ever-shallower, low-resistivity junctions. It is desirable to form these junctions using ion implantation and rapid thermal annealing (RTA) which has the ability to activate the implanted impurities for electricity conduction in silicon and remove implant damage sufficiently. For example, the conventional method of forming source/drain regions and/or source/drain extension regions involves implanting boron ions as p-type dopants or phosphorous ions as n-type dopants. The implantation is performed at low energy levels to achieve a shallow junction depth. The resulting structure is then annealed, typically at about 1000° C.˜1050° C. to activate dopants. However, the conventional use of RTA for the duration of several seconds has a high thermal budget that would inevitably result in additional dopant diffusion and hence restrict silicon device downscaling. In addition, achievement of a small junction depth is problematic, especially for a p+ region formed using boron ions. It has been found that during dopant activation anneal, boron diffusion in the crystalline silicon layer is significantly large, so that the junction depth of the boron tends to be much deeper than planned. The RTA technique, typically includes quickly raising the temperature of the wafer and holding it at that temperature for a time long enough to successfully perform a fabrication process, while avoiding such problems as unwanted dopant diffusion that would otherwise occur at the high processing temperatures.
What is needed in the art, therefore, is a novel thermal approach for enhancing dopant activation and maintaining low thermal budget simultaneously to minimize dopant diffusion.